Serial storage architecture (SSA) is a serial interface which provides a flexible addressing scheme to allow the configuration of a web of two or more nodes into a loop or string configuration. The nodes are interconnected by links or switches. The nodes can be SSA combined with disk, optical, tape or CD-ROM drives, or printers. These nodes are known as "targets." A node can also be SSA integrated on a host adapter. The host adapter is typically associated with a computer, and this configuration is referred to as an "initiator." The web supports node-to-node (peer-to-peer) communication with information multiplexing between any pair of nodes. The link provides point-to-point physical connection between nodes. A standard link protocol allows operation at 20 MBytes/sec over distances up to 600 meters between nodes.
Multiple links can create strings or loops of nodes if the nodes utilize dual ports with cut-through routing. Each link provides full-duplex communication so that each port transmits on an outbound line subject to information received on an inbound line. The link is capable of a peak data rate of 20 MBytes/sec in each direction for a 40 MBytes/sec total bandwidth per port.
A unit of information transferred over a link is a "frame." There are three types of frames: control, privileged and application. Each frame contains a control, an address, a data and a CRC field. A control field, one byte long, is used to identify the type of frame and the frame sequence number. The address field, from one to six bytes long, is used to route the frame to a destination node and to select the appropriate channel to a microprocessor, DMA or outbound port via cut-through. The data field, from zero to 128 bytes, provides information such as data, messages, etc. The CRC field, four bytes long, contains frame parity and end-of-frame data.
One SSA configuration, as illustrated in FIG. 1, utilizes a single buffer RAM 10 for both ports 12, 14. RAM 10 has inbound and outbound buffers that are dedicated to each of ports 12, 14. As frames arrive from SSA links 16 and 18 to ports 12, 14, they are routed to an inbound buffer for that respective port. The frame is then routed from the inbound buffer to one of several destinations, such as the other port, to firmware associated with a microprocessor .mu.P via lead 20, or to a local DMA channel also via lead 20. Concurrently, buffers are being filled with frames by the local DMA channel or the firmware to be sent outbound across the link 16 or 18.
RAM 10 must support 20 MBytes/sec for each of the four leads of bus 22 and 40 Mbytes/sec on lead 20. This translates to a total bandwidth of 120 MBytes/sec that RAM 10 must support. In addition, one or more DMA channels, DMA SMS automation channels and a firmware channel can require guaranteed buffer access. Thus, RAM 10 must be correspondingly fast. Such a fast RAM needs an increased area due to a wider data path or double-banked structure. This will increase the cost of RAM 10 accordingly. Transfer rates for each of the four leads of bus 22 and lead 20 can increase to 40 MBytes/sec, for example. RAM 10 would therefore need a further increase in area, which would result in a further increase in cost.
The double-banked structure has two arrays which are typically accessed alternately to achieve maximum bandwidth. A disadvantage of this structure is that all channels may not have guaranteed access. For example, a first port channel is given access to RAM 10 by a time-multiplexed slot arbiter. A second port then requests access to RAM 10. However, the second port that requests the access requires access to the array that the first port accessed. Since the double-banked structure must access the other non-requested array before allowing access to the requested array, the second port access is delayed to the requested array. The history of the RAM 10 access can affect future access time. Consequently, that effect limits the bandwidth of RAM 10. It may be possible to have an architecture for the double-banked structure to overcome this, but that architecture would be required to provide guaranteed access to all channels at the required bandwidth while maintaining the alternate access of the arrays. Such an architecture would be more complex than the architecture presently known, and would therefore be more expensive and require more chip area.
A further disadvantage of the FIG. 1 configuration is that, typically, there is a need for more inbound buffers than outbound buffers. However, the FIG. 1 configuration uses two dedicated inbound and two dedicated outbound buffers per port. With this scheme, the outbound buffers can be inactive. For example, if the internal DMA channels are either inactive or are servicing write commands from a port, then the two outbound buffers for this port are idle. That scheme does not provide for the use of the idle outbound buffers, where such use could benefit the transfer rate of the inbound frames. Further, this scheme may not provide optimal transfer rates for different environments that use an SSA serial interface.
Therefore, there exists a need for an SSA serial interface that can support increased data rates, different environments and expansion without a corresponding substantial increase in cost, and can utilize available memory more efficiently to provide better transfer rates. The present invention meets this need.